Last modified by Leon Luo on 2022/07/30 14:58

Setup and Hold Times

When clocking on the triggering edge for a flip-flop, there's some rules that must be followed.

  • You must have your data input to the flip-flop stable for a certain amount of time before the clock's triggering edge occurs. This time is called the setup time.
  • You must have your data input to the flip-flop stable for a certain amount of time after the clock's triggering edge occurs. This time is called the hold time.

By violating these rules (such as changing your data input as you're clocking the triggering edge), issues will arise, in which you'd generally want to avoid at all costs. There are however some cases where you just can't avoid them. This is where the next section comes in.


TL:DR: Changing the input of a flip-flop while the clock is on the triggering edge can make the output voltage between high and low for an undefined amount of time, causing havoc down the line. Cascade an extra flip-flop afterwards on the same clock to drastically reduce the chance of this happening. Such asynchronous inputs include everything that doesn't run on the exact same clock inside the FPGA, like all external inputs.

Imagine you had a D Flip-Flop (falling edge-triggered). It has Data input, Clock input, and Q output. Let's say your clock performs a falling edge change while your Data input is also changing at roughly the same time. What will the output Q be? High? Low? Something in between?

Well, the answer is it can be any of the mentioned 3. Yes, the output can even be some voltage between high and low. Why though? How though?

In real life, clock transitions and even signal levels don't change at an instant. They may change quickly, but on a waveform chart, a non-perpendicular line exists between the previous voltage level to the next voltage level, usually characterised by something called slew rate measured in volts per second.

As you might have learnt in ELEC2141, a D flip-flop is constructed of two cascaded D latches, one activated on the inverted level of the other. In a way, this "samples" the input voltage when the clock changes one of the edges (in this example, it's a falling edge). You might have remembered that a D latch is also made of an SR latch, which can have an invalid state if both the Set input and Reset input are high (or high if they're inverted inputs).

Going back to the D flip-flop, as you change the Data input, it is possible to put the SR latch within in the invalid state for a brief amount of time. Normally this is fine, but if you perform the triggering edge while this occurs, both the Set input and Reset input of the internal SR latch can potentially go low (or high if they're inverted inputs) at the same time. So what does the SR latch do in this case? Quite the puzzling question, but depending on many factors including noise, gain and how the latch is structured physically, it can be high, low, or a voltage in between. The latter undesired state occurs because the latch "can't figure out" which one wins, so the internal transistors basically become a voltage divider.

This is an example of metastability, because it's a stable in-between state. It's a artefact of trying to discretise physics that is continuous. Imagine all your circuitry down the line; you have one output that has some voltage that's halfway between high and low, and everything else takes that input, or takes something that takes that input. Absolute chaos! Increased power consumption too such that your chip might blow up! Now luckily this doesn't happen forever. Despite being in this weird middle state, it will eventually resolve to a valid logic level after an undefined amount of time (a random one which sucks but better than nothing). So luckily, it's not necessarily stable forever.

Try this at home. See if you can balance a pencil on it's tip. Give it a couple tries! In your bad attempts, the pencil will probably fall quite quickly, but in your good attempts, your pencil might stay still for a while, but fall over eventually. It's kind of like that here, where falling over is the stable high or low state, while it being balanced is the metastable somewhere-in-between state.

So how do we ensure it will resolve?

Well... you can't. Bummer, because as I said, it can last for an undefined amount of time. However, you can drastically increase the chance of it resolving!

Since in the vast majority of cases, the output will resolve pretty quickly, all you have to do is just wait for this to happen. You can simply do this by cascading an extra D Flip-flop afterwards to create a delay (which might suck but deal with it). Make sure the data line between doesn't go through anything else, and isn't connected to anything else. Also make sure the data line is as short as possible, since signals have travel time, which will eat into the delay time your extra D Flip-Flop created. In Xilinx FPGAs, there's an attribute ASYNC_REG you can add to specify the D Flip-flops (registers) are asynchronous, which will indicate routing to put the registers as close to each other as possible (some other FPGA manufacturers don't have this because they suck). If you're making some aeronautical, military, or medical device, perhaps this vast improvement isn't enough1. How to make it better? Well you can just cascade another one! Even 2 or as many to your heart's content. Just saying, by this point, you'll be reducing the chance so much that it will not happen within the lifetime of the universe. 1 extra flip-flop is usually enough.

1This might also be necessary for more normal situations, maybe ones involving higher clock speeds but I'm not good enough to elaborate as there's likely way more factors to determine this.

Written by Bradley Lin


Xilinx XAPP077 and Xilinx XAPP094

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