ELEC2141 - Digital Circuit Design
Study Level and UNSW Handbook
Undergraduate - ELEC2141
Requisite Courses
Co - ELEC1111
Contents
Overview
Concepts
Disclaimer
Digital Systems Fundamentals
Combinational Logic
Analysis
Design
Sequential Logic
Analysis
Design
Digital Arithmetic
Computer Design Fundamentals
Digital Integrated Circuit Technologies
Hardware Description Language (HDL)
Timescale
a "#" symbol is used to specify the propagation delay, such as #100; (this will be mentioned later)
Each verilog code starts with timescale
timescale represents the propagation delay units, in this case:
- 1ns is the unit of the delay
- 1ps is the precision
Module Declaration
the syntax of a module is written below
//some operation of your desire
endmodule
with a few notes in mind, a module is like an IC chip you designed
- name_of_module : The name you decide to give your "chip".
- It is composed of alphanumeric characters and underscores ( _ )
- they must start with letters of alphabet
- port : like the pins of the "chip", with inputs and outputs
- parenthesis (brackets) must be terminated with a semicolon
Initially, the module must have input, output and wire inside the module declared.
output P;
input A, B, C;
wire W1, W2, W3;
//some desired operation
end_module
A few new keywords in this code snipper these are the process of declaration where we define ports and wires.
- output : port that would be output of the module
- input : port that would be input of the module
- wire : declaring any wire that will be used in the module
There are 12 predefined modules, including: and, or, not, nor, nand, xor, xand, buf
Using a Module
Each Module must be written in a seperate file!
Lets say you made a module called "my_module", now to use it somewhere
Syntax of using a module called my_module
with a few notes
- my_module is the module name, it's what you name your module.
- instance_name is the name of that particular module
- port is the wire connecting to the port of the module, wires should be defined.
this is called instantiation, where we use the module and give it a name.
to be confused with declaration, instantiation uses what is declared.
a little analogy here would be like
Human Pete (B, C, E, F) ;
Immortal Cool_Joe (A, B, E, F) ;
a module is usually used inside other modules, such as the my_module below
to represent above in verilog
output p, q;
input a, b, c, d;
wire w1;
and A1 (w1, a, b);
and A2 (q, c, d);
or B1 (w1, q, p);
endmodule
Propagation delay
as mentioned earlier, propagation delay is implemented by #, can be used to simulate a delay
output p, q;
input a, b, c, d;
wire w1;
and #(20) A1 (w1, a, b);
and #(20) A2 (q, c, d);
or #(30) B1 (w1, q, p);
endmodule
This simulates an actual circuit which module may have propagation delays.
output p, q;
input a, b, c, d;
wire w1;
and #(20) A1 (w1, a, b);
and #(20) A2 (q, c, d);
or #(30) B1 (w1, q, p);
endmodule
Vectors
Vectors are identifiers with multiple bits wide. Below shows an example with a decoder module
output d[3:0];
input a, b, E; // is the enable input
wire w1, w2, w3;
not G1(b, w1) G2(a, w2);
and G3(d[3], a, b, E) G4(d[2], a, w1, E) G5(d[1], w2, b, E) G6(d[0], w1, w2, E);
endmodule
Things to note
- The left most is always the most significant bit (it is prioritised)
- Output can be accessed individually with [ ] with the number in it
Test Bench
A test bench provides signals and lets output to be measured with iSims.
- test bench, unlike modules, have no parenthesis for inputs and outputs
- test bench inputs must be declared with keyword "reg"
- "reg"y to start yet?
- test bench output must be declared with keyword "wire"
- "wire" you not done?
Below shows an example of test_bench "module"
reg input1, input2, input3, input4;
wire output1, output2;
my_module_with_delay (input1, input2, input3, input4, output1, output2)
//things that we will talk about later on
end_module
Numbers in Verilog
We will then have to use begin .. end to execute statement.
- # is used for delay
- 1'b0 represents 0 in binary while 1'b1 represents 1 in binary
- $finish terminates system task
reg input1, input2, input3, input4;
wire output1, output2;
my_module_with_delay (input1, input2, input3, input4, output1, output2);
initial
begin
input1 = 1'b0;
input2 = 1'b0;
input3 = 1'b0;
input4 = 1'b0;
#100;
input1 = 1'b1;
#100;
input1 = 1'b0
input2 = 1'b1;
//do whatever you want the input to do onwards
end
initial;
end_module
Syntax of numbers in Verilog are represented by the following
3'b110
- 3 is the number of digits in the number
- b, represents binary. d for decimal, h for hexadecimal
- 110 represents the actual number
these numbers can be used with vectors
reg[0:3] input;
wire output1, output2;
my_module_with_delay instance_name (input[0], input[1], input[2], input[3], output1, output2);
initial
begin
input = 4'b0000;
#100;
input = input + 4'b001;
#100;
input = input + 4'b001;
#100;
input = input + 4'b001;
#100;
input = input + 4'b001;
#100;
//do whatever you want the input to do onwards
end
initial;
end_module
Repeat Function
The repeat function repeats the next line a number of times. The number of times is inside the parenthesis of the function.
With this, we can write things with less line of code.
reg[0:3] input;
wire output1, output2;
my_module_with_delay instance_name (input[0], input[1], input[2], input[3], output1, output2);
initial
begin
input = 4'b0000;
repeat(15) #100 input = input + 4'b001;
//do whatever you want the input to do onwards
end
initial;
end_module
Dataflow Modelling (keyword assign)
Sike! All of the pre-defined modules, with and, or, not etc. can be replaced with easier notations!
keyword assign literally assigns values to what you give them.
with the following operators
- //subtraction
& //AND
| //OR
~ //NOT
^ //XOR
< //less then
> //greater then
== //equals to
{} //concentate
This is very intuitive, example is shown as below
Behavioural Modelling (keyword always)
perform HDL at a functional and algorithmic level
output of procedural statement is always reg. NOT wire.
keyword always runs the code inside it whenever a condition is triggered
// some code
end
"always" doesn't have semi-colons behind it as code following it can be comprehended
The condition can also be posedge and negedge
following snippet shows the condition
// code that will run when trigger changes value
end
always @ ( posedge trigger ) // "trigger" is a variable
// code that will run when
// trigger changes value at positive edge
end
always @ ( negedge trigger ) // "trigger" is a variable
// code that will run when
// trigger changes value at negative edge
end
If else statement
if else statement works like C. With a slightly different syntax
else fat = 0;
// generally
if ( /* condition */ ) /* some code */ ;
else /* some code */ ;
blocking (=) vs non-blocking (<=)
= to be confused with <=
= is a blocking statement. It's line will run after the previous line.
<= is a non blocking statement. It will run in parallel with the previous line.
// to be the original value of b
always @ (posedge trigger)
a = b;
b = a;
end
// the following will result in both a to be
// original value of b and vice versa
always @ (posedge trigger)
a <= b;
b <= a;
end
Recommended Resources
Course Prescribed
Textbook
- M. Mano, C. R. Kime and T. Martin, Logic and Computer Design Fundamentals, 5th Edition (Global Edition), Pearson, 2016
Course Recommended
Textbook
- M. Mano, C. R. Kime, Logic and Computer Design Fundamentals, 4th Edition, Prentice Hall, 2008
- R. H. Katz & G. Borriello, Contemporary Logic Design, 2nd Edition, Prentice Hall, 2005
- M. Mano & M. D. Cilietti, Digital Design, 4th Edition, Prentice Hall, 2007
- J. F. Wakerly, Digital Design: Principles and Practices, 4th Edition, Prentice Hall, 2006